Performance Analysis of Clock Distribution Networks for Application in System on Chip

In synchronous digital systems, a clock is defined as the periodic synchronization signal used as a time reference for data transfers. This clock signal must be available at each flip flop, latch, counter etc. of an integrated circuit so that these elements may perform synchronized functions. This synchronization is done with the help of Clock distribution networks and hence they are an important part of synchronous circuits. This clock distribution networks significance is such that it finds applications in systems ranging in size from medium scale circuits to large multimillion transistor microprocessors and ultra-high-speed computers fully utilize this synchronous operation. Despite significant advances in the last decade, modern clock distribution faces practical design problems as well as performance limitations thus necessitating a high efficient clock networks for reliable operation of Integrated circuits. This paper makes use of LT spice XVII in designing the schematics and simulation of different categories clock distribution networks. Keywords - Clock distribution network, System-on-chip (SoC), clock skew, clock jitter, Buffers, Tree, Grid.