Design And Verification Of Network-On-Chip Router Architecture
The scaling of microchip technologies has enabled large scale system-on-chip (SoC). Network-on-chip (NoC)
research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric
design and (ii) the implementation of scalable communication structures. NoC designs are based on compromise of latency
and power dissipation usually defined at design time. In this paper, a novel cost-effective and low-latency wormhole router
for packet switched NoC design has been proposed.
Keywords- Network-on-Chip, Router, Arbiter, GALS.