Design And Simulation Of Low Power And Area Efficient 32 Bit Multiplier
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters,
digital signal processors and microprocessors etc. Speed of a system depends upon how a faster an arithmetic operations are
performed within the structure for which mostly multiplication should be carried out at a faster rate which thus improves the
system performance. The area and speed of the multiplier is an important issue, increment in speed results in large area
consumption and vice versa.
Multipliers are one of the most important building blocks in processors. Multipliers are of great significance in today’s
Digital Signal processing applications like DFT, IDFT, FFT, IFFT and ALU in Microprocessor. The two high speed
multipliers, Modified booth multiplier (MBM) and the Wallace tree multiplier are hybridized with Carry Look Ahead adder
(CLA) and formed a hybridized multiplier which delivers high speed computation with low power consumption. MBM is
proposed to reduce the partial products whereas Wallace tree multiplier is accompanied for fast addition and CLA is used for
final accumulation. This hybrid multiplier produces better results in terms of speed and power than the conventional designs.
The various results mentioned in paper are discussed. This work evaluates the performance of the proposed designs in terms
of delay, area, power and their products by hand with logical effort and through custom design.
Keywords- Carry select adder, Wallace Tree, Booth Encoder, Unsigned multiplier, Carry Save Adder.