International Journal of Advance Computational Engineering and Networking (IJACEN)
.
Follow Us On :
current issues
Volume-10,Issue-4  ( Apr, 2022 )
Past issues
  1. Volume-10,Issue-3  ( Mar, 2022 )
  2. Volume-10,Issue-2  ( Feb, 2022 )
  3. Volume-10,Issue-1  ( Jan, 2022 )
  4. Volume-9,Issue-12  ( Dec, 2021 )
  5. Volume-9,Issue-11  ( Nov, 2021 )
  6. Volume-9,Issue-10  ( Oct, 2021 )
  7. Volume-9,Issue-9  ( Sep, 2021 )
  8. Volume-9,Issue-8  ( Aug, 2021 )
  9. Volume-9,Issue-7  ( Jul, 2021 )
  10. Volume-9,Issue-6  ( Jun, 2021 )

Statistics report
Jun. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 112
Paper Published : 1361
No. of Authors : 3438
  Journal Paper


Paper Title :
Design and Development of I2C Protocol Using VERILOG

Author :Sireesha Bhuvanagiri, Shaik Khasim Beebi

Article Citation :Sireesha Bhuvanagiri ,Shaik Khasim Beebi , (2017 ) " Design and Development of I2C Protocol Using VERILOG " , International Journal of Advance Computational Engineering and Networking (IJACEN) , pp. 22-25, Volume-5, Issue-4

Abstract : The I2C protocol was given by the Philips Semiconductors in order to allow faster devices to communicate with slower devices and also allow devices to communicate with each other over a serial data bus without data loss. I2C plays an important role as an interface in communication between devices. Electrically Erasable Programmable Read Only Memory (EEPROM), Analog to Digital Converter (ADC), Digital to Analog Converter (DAC) and Real Time Clock (RTC) requires an interface for communication and I2C is used as an interface between them. In this paper, the I2C (Inter-Integrated Circuit; generically referred to as "two-wire interface") is implemented using Verilog with Field Programmable Gate Arrays (FPGA). The I2C master bus controller was interfaced with Alter DE1 board, which act as a slave. This module was designed in Verilog HDL and simulated in Modelsim 10.1c. The design was synthesized using Quartus 11 10.1 tool. Today, testing and verification are alternatively used for the same thing. Testing of a large design using FPGA consumes longer compilation time in case of debugging and committing small mistakes. Keywords - Altera DE1 Board, System Verilog, I2C bus , SDA, SCL.

Type : Research paper

Published : Volume-5, Issue-4


DOIONLINE NO - IJACEN-IRAJ-DOIONLINE-7623   View Here

Copyright: © Institute of Research and Journals

| PDF |
Viewed - 61
| Published on 2017-06-19
   
   
IRAJ Other Journals
IJACEN updates
Paper Submission is open now for upcoming Issue.
The Conference World

JOURNAL SUPPORTED BY