Paper Title :Pipelined Routing Network For Multiprocessor System On Chip
Author :B.Sree Lekha, G.Dilli Rani, V Thrimurthulu
Article Citation :B.Sree Lekha ,G.Dilli Rani ,V Thrimurthulu ,
(2014 ) " Pipelined Routing Network For Multiprocessor System On Chip " ,
International Journal of Advance Computational Engineering and Networking (IJACEN) ,
pp. 1-5,
Volume-2,Issue-10
Abstract : This paper presents the silicon-proven design of a novel On-chip interconnection networks or Network-on Chips
(NoCs) are becoming the de-facto scaling communication techniques in Multi-Processor System-on-Chip (MPSoC) or Chip
Multiprocessor (CMP) environment. The proposed network design configured with a 25-bit data width is synthesized and
implemented in a 0.13-µm CMOS STD-cell technology.The proposed network employs a pipelined circuit-switching
approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup
scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a
guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. A test chip
comprised of 25 testing tiles is designed to test the network. Each testing tile has a 50-bit RISC and FIFO-based test
wrappers interfaced with the proposed on-chip network. Tools required Modelsim 6.3 for Debugging and Xilinx 14.3 for
Synthesis and Hard Ware Implementation.
Type : Research paper
Published : Volume-2,Issue-10
DOIONLINE NO - IJACEN-IRAJ-DOIONLINE-1272
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Copyright: © Institute of Research and Journals
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Published on 2014-09-22 |
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