Paper Title :Implementation of 32-bit 5-stage Pipelined RISC Processor

Author :Nayana Yerram, Deepak Ch

Article Citation :Nayana Yerram ,Deepak Ch , (2021 ) " Implementation of 32-bit 5-stage Pipelined RISC Processor " , International Journal of Advance Computational Engineering and Networking (IJACEN) , pp. 1-4, Volume-9,Issue-6

Abstract : A Reduced Instruction Set Computer or RISC has a small set of simple instruction exist in 8,16,32 and 64-bit, which are now used across a wide range of platforms. The low power technique, Pipelining is the process of executing the instructions in the orderly fashion. In this paper, 32-bit 5-stage pipelined RISC Processor is designed utilizing Verilog HDL. The objective of this paper is to execute 32-bit instructions set which is written using hardware description language (HDL) in pipeline process to lessen the power utilization. The processor is designed on Xilinx ISE Design Suite platform. Keywords - Reduced Instruction Set Computer (RISC), Low Power, Pipelining.

Type : Research paper

Published : Volume-9,Issue-6

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