International Journal of Advance Computational Engineering and Networking (IJACEN)
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Statistics report
Jan. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 82
Paper Published : 1209
No. of Authors : 3038
  Journal Paper

Paper Title
Design And Verification Of Network-On-Chip Router Architecture

Abstract
The scaling of microchip technologies has enabled large scale system-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. NoC designs are based on compromise of latency and power dissipation usually defined at design time. In this paper, a novel cost-effective and low-latency wormhole router for packet switched NoC design has been proposed. Keywords- Network-on-Chip, Router, Arbiter, GALS.


Author - Deepak S, Divyaprabha, M Z Kurian

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| Published on 2015-09-03
   
   
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