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  Journal Paper


Paper Title :
Design And Verification Of Network-On-Chip Router Architecture

Author :Deepak S, Divyaprabha, M Z Kurian

Article Citation :Deepak S ,Divyaprabha ,M Z Kurian , (2015 ) " Design And Verification Of Network-On-Chip Router Architecture " , International Journal of Advance Computational Engineering and Networking (IJACEN) , pp. 73-76, Volume-3, Issue-9

Abstract : The scaling of microchip technologies has enabled large scale system-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. NoC designs are based on compromise of latency and power dissipation usually defined at design time. In this paper, a novel cost-effective and low-latency wormhole router for packet switched NoC design has been proposed. Keywords- Network-on-Chip, Router, Arbiter, GALS.

Type : Research paper

Published : Volume-3, Issue-9


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